The fabrication of field effect transistors (FETs) can involve the formation of a silicon nitride (Si3N4) cap atop a gate stack including gate electrode and gate dielectric layers. The silicon nitride cap is added to the top of the gate stack during the stack deposition process and must remain sufficiently intact after patterning the same so as to impede epitaxial growth of semiconductor materials at the top of the gate stack during formation of source/drain regions. Silicon germanium (SiGe) and carbon doped silicon (Si:C) are among the materials employed for forming source/drain regions of silicon-based pFET and nFET devices, respectively. Subsequent to formation of source/drain regions, the nitride cap must be fully removed from the gate stack without damaging exposed portions of the source/drain regions. Wafer wide removal can be attempted using conventional chemistries, for example CH3F/O2 (fluorohydrocarbon) and low ion energy platforms such as the TEL (Tokyo Electron Limited) RLSA (radial line slot antenna) and Lam Research KIYO® conductor etch system. A fluorohydrocarbon plasma employed for anisotropic etching of silicon nitride is selective to silicon oxide. Selectivity to silicon, while not inherent, is based on the formation of silicon oxide on silicon, thereby preventing further erosion of the silicon. High selectivity to silicon at the nanoscale level is not obtained using such technology. The removal of the nitride cap while avoiding damage to the gate and/or the source/drain regions in an efficient and effective manner is a goal of those in the semiconductor processing industry.
Some types of field effect transistors (FETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. Such field effect transistors are referred to as FinFETs. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged.